(1) Field of the Invention
The present invention relates to an intermittent operation circuit for intermittently operating a CPU or the like to attain a low consuming power in a computer peripheral device.
(2) Description of the Prior Art
FIG. 7 is a block diagram illustrating a conventional intermittent operation circuit. In FIG. 7, the reference numeral 1 designates a single chip microcomputer, 2 an oscillator, and 3 an oscillation circuit. An internal clock oscillating means for generating an internal clock is composed of the oscillation circuit 3 and the oscillator 2.
The reference numeral 4 designates a CPU which operates in synchronism with the internal clock signal generated by the oscillating circuit 3, 5 a timer which divides an internal clock signal generated by the oscillation circuit 3 and counts the divided clocks, and generates a timer interruption in the CPU 4 in a state where the count value is reduced to lead to an underflow, 6 a switch which connects the oscillation circuit 3 to the CPU 4, and 7 a switch which connects the oscillation circuit 3 to the timer 5.
The operation of the intermittent operation circuit will now be described.
When, the microcomputer 1 is in the normal operation mode, the switches 6 and 7 are in the ON state and the oscillation circuit 3 is in the operation mode. Accordingly, an internal clock signal is always supplied from the oscillation circuit 3 to the CPU 4 and the timer 5, so that the operation mode is maintained.
Nevertheless, depending on the employed system, the CPU 4 is not always required to operate. Rather, there is a case in which it is sufficient that the CPU 4 operates intermittently at a constant time interval. Therefore, if the CPU 4 is operated intermittently at a constant period and the operation of the CPU 4 is stopped at other periods, the consuming power of the system can be reduced.
In this prior art, the CPU 4 repeats the operation mode and the stop mode (low consuming power mode) at a constant period as shown in FIG. 8. To carry out this repetition in a case where the operation is transferred to the stop mode, the switch 6 is turned to the OFF state when the CPU 4 finishes the operating mode as shown in FIG. 9. This operation is hereinafter referred to as an execution of the power off instruction A.
After this, the internal clock signal is not supplied from the oscillation circuit 3 to the CPU 4, so that the CPU 4 is switched to the stop mode. However, in this case, the switch 7 maintains the ON state and the internal clock is supplied from the oscillation circuit 3 to the timer 5, thereby maintaining the operation mode.
Then, when the CPU 4 is switched to the stop mode, the timer 5 divides the internal clock signal supplied from the oscillation circuit 3 and starts counting the divided signal. When the count value is reduced to lead to an underflow, that is, when a period T2 has passed after the CPU 4 is switched to the stop mode, the switch 6 is turned to the ON state and a timer interruption is generated in the CPU 4, whereby the operation of the CPU 4 is restored. Consequently, the CPU 4 is switched to the operation mode again, so that the intermittent operation of the CPU 4 is attained.
As shown in FIG. 9, in a case where the switch 6 is turned to the OFF state, and simultaneously the switch 7 is turned to the OFF state and the operation of the oscillation circuit 3 is stopped (these three simultaneous operations are hereinafter referred to as the execution of the power off instruction B), the operation of the timer 5 can also be stopped. Therefore, the consuming power in the execution of the power off instruction B can be further reduced than in the execution of the power off instruction A. However, when the power off instruction B is executed, a timer interruption cannot be generated from the timer 5 so that the operation of the CPU 4 cannot be restored and the intermittent operation of the CPU 4 cannot be attained.
A conventional intermittent operation circuit is so constructed as described above. Hence, the timer 6 and the oscillation circuit 3 must be operated at all times to attain the intermittent operation of the CPU 4. Therefore, there is a problem in that the consuming power of the circuit system cannot be significantly decreased.